The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the present invention relates to improved techniques for performing planarization and recess etches during the manufacture of integrated circuits, which advantageously minimizes costs, device damage due to charging, and improves throughput.
The sequence of planarization and recess etches is required in the manufacture of a variety of integrated circuits (ICs). By way of example, in the manufacture of dynamic random access memory (DRAM) integrated circuits, trench capacitors may be formed by repeated sequences of deposition, chemical-mechanical planarization, and recess etch. To facilitate discussion, FIGS. 1-3 illustrate a simplified sequence of deposition, chemical-mechanical planarization, and recess etch that may be employed in the prior art to fabricate a trench capacitor in a DRAM. Referring initially to FIG. 1, a substrate 102, typically comprising silicon, is thermally oxidized to form a layer of silicon dioxide (SiO.sub.2) 104 (which may be about 10 nm thick). Above oxide layer 104, a layer of silicon nitride 106 is blanket deposited.
A conventional photoresist mask is then formed on the surface of the substrate to facilitate etching trench 108 in substrate 102 through silicon nitride layer 106 and oxide layer 104. After the photoresist mask is removed, a polysilicon fill step is employed to deposit polysilicon over the top surface of substrate 102 and into trench 108. In FIG. 1, this polysilicon fill layer is shown as polysilicon layer 110. To facilitate the subsequent recess etch of the polysilicon material in trench 108 and to planarize the top surface of polysilicon layer 110, a chemical-mechanical polish (CMP) step may be performed next. The CMP of polysilicon layer 110 typically employs silicon nitride layer 106 as a CMP etch stop.
In FIG. 2, polysilicon layer 110 has been planarized down to the top surface of silicon nitride layer 106. However, a column of polysilicon material remains in trench 108. Subsequently, a reactive ion etching (RIE) etch step is employed to recess etch the polysilicon column within trench 108.
In FIG. 3, the RIE etch has removed a portion of the polysilicon column within trench 108. The photoresist mask has also been removed in FIG. 3. As can be seen in FIGS. 1-3, after the sequence of deposition (FIG. 1) chemical-mechanical planarization (FIG. 2) and recess etch (FIG. 3), a polysilicon plug is formed within trench 108. The sequence of deposition, chemical-mechanical planarization, and recess etch may be repeated multiple times to facilitate the formation of the trench capacitor.
There are, however, disadvantages associated with the sequence of deposition, chemical-mechanical planarization, and recess etch described in FIGS. 1-3. By way of example, the use of a CMP step to planarize polysilicon layer 110 may at times causes dishing into the trench (i.e., a slight depression into the trench), which results in a loss of recess depth control and process difficulties at later stages. The dishing effect may be seen in FIG. 2, which shows a depression over the silicon plug in trench 108.
The CMP step also has a low selectivity to nitride and causes erosion of pad nitride layer 106. If silicon nitride layer 106 is employed as the CMP etch stop for multiple CMP steps, an excessive amount of nitride erosion may result, possibly rendering the device defective. Further, the CMP etch step may cause nonuniform erosion of silicon nitride layer 106, which also causes difficulties in subsequent process steps. CMP is also widely known as an expensive process, i.e., it disadvantageously requires costly tools and reduces wafer throughput. The CMP process also disadvantageously generates particulate contamination in the form of a slurry, which requires time-consuming cleaning and drying steps afterward.
Not only is the prior art CMP step expensive, the reactive ion etching (RIE) step employed to recess etch the polysilicon column in trench 108 also requires its own costly RIE tools. The use of a RIE technique to recess etch the polysilicon material in trench 108 also causes additional and/or nonuniform erosion of silicon nitride layer 106 since the RIE etch tends to be a physical etch in which the bombarding ions tend to have a low selectivity to nitride.
Conventional recess etch techniques that have a good selectivity to nitride also have their problems. For example, although isotropic etch techniques (i.e., those which employ the reactive neutrals as the main etching mechanism) tend to have good selectivity to nitride, these isotropic etch processes tend to result in the amplification of voids or seams in the polysilicon column within trench 108. This is because the polysilicon fill step that forms polysilicon layer 110 in FIG. 1 may create seams or voids in trench 108 if the polysilicon deposition process is not carefully designed or if the aspect ratio of trench 108 is particularly aggressive. The seam or void is shown in FIG. 4 as a void 402. If a purely or dominantly isotropic tool is subsequently employed to recess the polysilicon column in trench 108, lateral attack (which is caused by the presence of the neutral species in the plasma of the isotropic etch) may amplify the void, causing a loss of depth control during the recess etch. To illustrate the foregoing, the lateral attack mechanism is depicted in FIG. 5 in which void 402 is amplified due to the isotropic etch action of the reactive neutral species present in the plasma of the isotropic etch step.
As can be appreciated from the foregoing, there are desired improved techniques for performing the planarization/recess etch sequence which advantageously offers a high degree of etch depth control while minimizing erosion to the silicon nitride layer. The improved techniques and apparatus therefor preferably accomplish the foregoing while minimizing costs, reducing device damage due to charging, and improving wafer throughput.